Electrical timing device

ABSTRACT

An electrical timing device comprising a capacitor, a timing resistor and a discharge circuit for the capacitor which is maintained ineffective as long as power supply is not interrupted. In a preferred application, the interval timed exceeds the change-over time of a bistable register, a priming signal applied to bias the register into a preferred state being terminated on the expiry of the interval.

United States Patent 1 Husbands et al.

[ 1 May8,1973

[54] ELECTRICAL TIMING DEVICE [75] Inventors: Keith Ronald FrederickHusbands,

Sandiacre; John Dawson, Kirby-in- Ashfield, both of England [73]Assignee: Plessey Handel Und Investments 22 Filed: June 22, 1971 21App1.No.: 155,545

[30] Foreign Application Priority Data July 14, 1970 Great Britain..34,159/7O [52] US. Cl. ..307/304, 307/202, 307/293, 307/296, 317/36TD, 321/45 S, 328/129 [51] Int. Cl. ..H03k 5/153 [58] Field of Search..307/202, 246, 293, 307/296, 297, 304; 317/36 TD; 320/1;

[56] References Cited UNITED STATES PATENTS 3,045,150 7/1962 Mann..307/293 X 3,189,751 6/1965 Winchel ..307/293 3,378,698 4/1968 Kadah...307/246 X 2,976,487 3/1961 Cohen ...307/293 X 3,158,790 11/1964Garratt ...328/129 X 3,383,623 5/1968 Vercellotti et a1 ...307/296 X3,449,655 6/1969 Jager 1 ..321/45 X 3,543,094 11/1970 South et al...317/36 TD Primary ExaminerStanley D. Miller, Jr. Assistant Examiner-R.C. Woodbridge AttorneyAlex Friedman et al.

[5 7] ABSTRACT 3 Claims, 5 Drawing Figures 2,942,123 6/1960 Schuh,.lr..307/293 L5 5 2 6 .9 V-k l m l- 1 L I i L ,L 1 W C 2* i j 44/ M2 I E I0/ g L l .I l? I l l L M P, l M3 5 20 l l t l:

| l l I a 3 {5 mi.

PATENTED MAY 8 I973 SHEET 1 [1F 5 QQLA ELECTRICAL TIMING DEVICE Thisinvention relates to electrical timing devices.

According to the invention there is provided an electrical timingdevice, responsive to the application of power to measure an interval oftime starting at the moment of application, which includes a chargingcircuit comprising a timing capacitor and a timing resistor connected inseries with each other, a discharge circuit by which the capacitor maybe discharged, and restraining means for maintaining the dischargecircuit in an ineffective state while power is applied to the device.The timing device is utilized in conjunction with an electrical plug-incircuit card carrying a circuit having at least one circuit elementcapable of assuming more than one state, which element must occupy apreferred one of said states before the circuit can be used. Primingbias circuit means delivers a signal responsive to said applied power toone of said elements to bias said one element to a preferred state, thedelivery of said signal being terminated in response to a switchingdevice in turn responsive to a switching signal produced by said timingdevice. Said switching signal is produced at a time interval exceedingthe time required for said one element to change from one to another ofsaid alternative states.

The invention will now be described in connection with its applicationto an electrical plug-in circuit card, and with reference to theaccompanying drawings in which:

FIG. 1 shows a first electrical plug-in circuit card carrying a timingdevice according to the invention,

FIG. 2 is a time chart used in explaining FIG. 1,

FIG. 3 shows a second electrical plug-in circuit card carrying amodification to the timing device shown in FIG. 1,

FIG. 4 shows a third electrical plug-in circuit card carrying a timingdevice according to the invention, and

FIG. 5 shows a fourth electrical plug-in circuit card carrying thetiming device shown in FIG. 3.

ln FIG. 1, the part of the drawing to the right of the chain line 1represents an electrical plug-in circuit card. The card has terminals 2,3, which form part of one half of a multiple plug-and-socket connector.The other half of the connector is fixed to a rack and offers furtherterminals 5, 6 which cooperate respectively with the terminals 2, 3,making physical and electrical contact therewith when the card isplugged in at a service position in the rack. In FIG. 1 only twoterminals in each half of the multiple connector are shown, but it is tobe understood that other terminals may be provided and used as requiredby the circuit carried on the card. Terminal 5 is connected to a sourceof reference potential, conveniently earth; and terminal 6 is connectedto a source of power potential, conveniently --24 volts.

The card carries an integrated circuit chip, the relevant parts of whichare shown to the right of the broken line 8. Electrical connection tothe chip is established by means of pads 9, catching diodes 10 beingprovided where necessary and connected to the chip substrate 1 1, thesubstrate 1 1 being connected to terminal 2.

The integrated circuit includes a bistable device comprising two MostsM1, M2 having their sources commoned, and their gates and drainscross-connected. The commoned sources of Mosts, M1, M2 are connectableover terminals 2, 5 to the source of earth potential. The drains ofMosts M1, M2 are connected respectively to the sources of two furtherMosts M3, M4 which serve passively as loads. The drains of Mosts M3, M4are connectable by terminals 3, 6 to the source of power potential. Thegates of Mosts M3, M4 are also connectable by terminals 3, 6 to thesource of power potential. The bistable device comprising the Mosts M1,M2 is responsive to input signals applied to the gate of Most M2 todeliver output signals from the drain of Most M2 as shown at 12, 13respectively. Mosts M1, M2 define a bistable register capable ofassuming two states. In normal operation, this device should occupy apreferred one of said states before the circuit can be used. Multiplepoints 14 are provided by which reference and power potentials may bedistributed as required within the chip. Multiple points 15 are providedby which these potentials may be distributed to other chips carried bythe card. When the card is plugged in at its service position on therack, reference potential appears at terminal 2 and power potentialappears at terminal 3. The bistable device M1, M2 assumes one of its twostable states arbitrarily. Let it be assumed that the Most M2 should beconducting before the integrated circuit can be brought into service.The requirement of placing the device in this preferred state is met inthe manner now to be described.

A timing capacitor C is connected in series with a timing resistor R1across the terminals 2, 3. At the junction of the capacitor andresistor, a lead 16 is provided by means of which the potential of thejunction is applied to the gate of a switching Most M5. The source ofMost M5 is connected to terminal 2. The drain of Most M5 is connected tothe source of a load Most M6 whose gate and drain are connected toterminal 3. A priming bias conductor 17 is run from the drain of theswitching Most M5 to the gate of a biasing Most M7, whose source anddrain are connected respectively to the source and drain of the Most M2of the bistable device M1, M2. A multiple point 18 allows for primingbias conductors being run in respect of other devices in the chip whichhave to occupy a preferred state of a number of alternative statesbefore the integrated circuit in the chip can be brought into service. Amultiple point 19 allows the potential of the lead 16 to be used inrespect of other chips carried by the card.

As soon as the card is plugged in at its service position in the rack,reference potential (earth) appears at terminal 2 and power potential(-24 volts) appears at terminal 3. The lead 16 assumes earth potential,preventing the switching Most MS from conducting. The load Mosts M3, M4,M6 all become conductive, causing negative potential to appear at thegates of Mosts, M1, M2, M7. The negative potential applied to the gateof Most M7 constitutes a priming bias signal which biases the bistabledevice M1, M2 into the state in which the Most M2 is conducting. Whilethe capacitor C starts to charge through resistor R1, the biasing MostM7 conducts and resolves the competition between the Mosts M1, M2 infavour of the Most M2, earth potential being delivered to the gate ofthe Most Ml. These events are illustrated in the time-voltage chart ofFIG. 2 where the vertical line 20 represents the instant of plugging-in.The thin horizontal lines to the left of the line 20 are trace lines forease of reference. The thick lines to the right of the line 20 depictthe events just described, and represent respectively:

I a. the potential at terminal 2, a

b. the potential at terminal 3,

c. the potential of lead 16, and

d. the potential of the priming bias conductor 17.

As the capacitor C continues to charge, the potential on lead 16 reachesa value which causes the switching Most M5 to conduct. This stage isrepresented by the line 21 in FIG. 2. When the Most M5 conducts, thepriming bias conductor 17 assumes earth potential. With its gate atearth potential, the biasing Most M7 becomes ineffective; the bistabledevice M1, M2 is left with the Most M2 conducting and is free to respondto input signals 12.

Once the switching Most MS has been operated, the charging processcontinues until the timing capacitor C is fully charged, as shown inFIG. 20. The timing capacitor C remains fully charged while the card isin service. if now the card is withdrawn from service, for example bywithdrawing the card from its service position or otherwise cutting offthe power supply, the bistable device M1, M2 is deprived of power. Whenpower is restored, it is fortuitous which of its alternative states isassumed by the bistable device M1, M2. Since the timing capacitor C isfully charged, the switching Most M5 is conductive and the delivery ofthe priming bias signal to the gate of Most M7 is prevented. To overcomethis difficulty, the timing capacitor C is provided with a dischargecircuit which becomes effective when the supply of power is interrupted.The discharge circuit comprises a discharge resistor R2 connected inseries with a diode D1 across the capacitor C, the resistor R2 beingconnected to the terminal 2. The diode D1 is poled so as to passdischarge current flowing from the timing capacitor C. When power isinterrupted, the capacitor C discharges through the diode D1 and thedischarge resistor R2. Hence, when power is resumed, a priming biassignal is developed on the priming bias conductor 17 as alreadydescribed. It is, however, necessary to prevent the discharge circuitfrom operating while the card is in service, an event which could impairperformance of circuits carried by the card. This unwanted discharge isprevented by a connection 20 run from the junction of the diode D1 anddischarge resistor R2 to the terminal 3. By the connection 20, thejunction is maintained at the potential of the terminal 3. And as longas the junction is maintained at the potential of the terminal 3, thetiming capacitor C is unable to discharge.

The value of the discharge resistor R2 is chosen so that the timingcapacitor C will discharge completely during any foreseeableinterruption to the power supply. Such interruptions may be due to anycause, including, in the case of plug-in circuit cards, contactbounceimmediately following the act of plugging the card in at a serviceposition. Contact-bounce, however, may be catered for in another way, aswill become apparent.

Considering now the charging of the timing capacitor C, it has alreadybeen explained that the operation of the switching Most M5 is deferredfor a time exceeding the change-over time of the bistable. device M1,M2. Contact-bounce can be catered for by deferring the operation of theswitching Most M5 for a longer period. This longer period slightlyexceeds the sum of the time required for the contacts to attainmechanical stability, and the change-over time of the bistable deviceM1, M2. The time required to attain mechanical stability can becalculated from the mechanical features of the contacts.

With integrated circuit chips it is known to employ two sources ofnegative potential in addition to a source of reference (earth)potential. The two sources are conveniently 12 volts and 24 volts. FIG.3 shows a circuit card having a chip which employs two sources ofnegative potential. The second source, i.e., l 2 volts is connectable tothe card by terminals 4, 7, and to the chip by a further pad 9.Components which have already been described in connection with FIG. 1are given the same references in FIG. 3 and are not described again. Todistribute the 12 volts supply, additional multiple points 14, 15 areprovided. When the card is plugged in, the bistable device M1, M2 is setto its preferred state as already described in connection with FIGS. 1,2. A second discharge circuit is provided comprising a dischargeresistor R3 connected in series with a diode D2 across the capacitor C;and a connection 21 between the junction of the diode D2 and thedischarge resistor R3 to the terminal 4. The diode D2 is poled so as topass discharge current flowing from the capacitor C. The seconddischarge circuit ensures that the charging process can only take placeif both the l 2 volt and the 24 volt supplies are uninterrupted.

Where the circuit on the card employs discrete components, thearrangement shown in FIG. 4 is adopted. Here again the componentsmounted on the card appear to the right of the chain line 1. Componentsthat function as described in connection with FIGS. 1, 2 bear thereferences accorded to them in FIG. 1. The card shown in FIG. 4 showstwo circuit elements which must occupy a preferred state before thecircuit carried by the card is brought into service. The first circuitelement is a flip-flop comprising two transistors T1, T2 having theiremitters connected-to the terminal 2, their bases and collectors crossconnected and their collectors connected by individual resistors R4, R5to the terminal 4. The first element responds to input signals deliveredat 12 to deliver output signals at 13. The second circuit elementcomprises a so-called square loop core 22 which can be magnetised in oneor other sense by an input pulse applied to one or other of the inputwindings 12a. When the core 22 is read out, an output pulse is deliveredat the output winding 13a.

To prime the flip-flop T1, T2 to the preferred state, I

which will be assumed to be when the transistor T2 is conducting, abiasing transistor T3 has its emitter and collector connectedrespectively to the emitter and collector of the transistor T2, and itsbase connected to the priming bias conductor 17. To prime the core 22 tothe preferred sense, a bias winding 23, wound in the sense of theappropriate input coil 12a, is connected across the terminals 2, 4 inseries with a biasing transistor T4 whose base is connected to thepriming bias conductor 17. The priming bias conductor 17 is connected tothe collector of a switching transistor T5, and, through a resistor R6,to the terminal 4. The emitter of the switching transistor T5 isconnected to the terminal 2. To achieve a positive switching action bythe switching transistor T5, the junction of the timing capacitor C andthe timing resistor R1 is connected to a zener diode Z, the outlet ofwhich is connected to the base of the transistor T5. The zener diode Zis biasedfrom a source of positive potential by way of further terminals24, 25 and a bias resistor R7. Multiple points 26 allow for thedistribution of reference and power potential to other componentscarried by the card. Multiple points 27 allow for the priming biassignal to be applied to other circuit elements which have to be primedto a preferred state.

The circuit works in a manner similar to that already described. Thebiasing transistors T3, T4 are conductive while the priming biasconductor 17 is maintained at negative potential. Negative potential ismaintained for a time sufficient for the first and second circuitelements T1, T2 and 22 respectively to assume their preferred states.Negative potential is terminated when the switching transistor T5 isswitched into conduction. This switching occurs when the potentialdeveloped by the timing capacitor C and timing resistor R1 causes thezener diode Z to break down.

In FIGS. 1, 3, a pad 9 has been shown individual to the switching MostM5. The need for this pad can be avoided by using simultaneously twoother pads which would not otherwise be used at the same time as eachother. Suppose the pads 9a, 9b carry respectively two consecutive timepulses ta, tb, which are delivered at co-operating terminals A,a; B,b.These pads are not normally used simultaneously. Instead of beingdirectly connected to the pads 9a, 9b, the terminals a, b are connectedas inputs to the respective one of two OR gates ga, gb. The junction ofthe capacitor C and resistor R1 is connected as an input to both of thegates ga, gb. The outlets of the gates ga, gb are taken respectively toinverters ma, mb and thence to the pads 9a, 9b. The gates ga, gb andinverters na, nb are made of discrete components. Within the chip, thepads 9a, 9b are connected respectively to the gates of two Mosts Ma, Mb.The two Mosts are connected in series with each other and with a loadMost Mc, and form an AND gate q. The outlet of the gate q is connectedto the gate of the switching Most M5. It will be seen that theapplication of the time pulses ta, tb is unaffected by this arrangement,and that the gate q does not respond to either time pulse alone. Theaction of plugging in causes negative potential to appear on the primingbias lead 17 as already described. After a suitable interval thejunction of the capacitor C and resistor R1 attains, on account of thecharging of the capacitor C, a value which switches both of the gatesga, gb, thereby opening the gate q and switching the Most M5. With themost M5 switched, earth potential is applied to the priming bias lead 17as already explained.

What is claimed is.

1. In combination with an electrical plug-in circuit card carrying acircuit having at least one circuit element capable of assuming morethan one state, which element must occupy a preferred one of said statesbefore the circuit can be used, which card also carries a first terminaland a second terminal at which reference and power potentialsrespectively appear when the card is plugged-in at a working position,the improvement which comprises at least one priming bias means forapplying a si a] responsive to said power potential from said seconterminal to at least one of said circuit elements to bias said oneelement to a preferred state; timing device means responsive to theappearance of said reference and power potentials at said first andsecond terminals respectively to time a time interval exceeding the timerequired for said one element to change from one to another of saidalternative states, and to produce a switching signal on the expirationof said time interval; and switching device means connected between saidpriming bias means and said timing device means for terminating thedelivery of said signal responsive to the power potential by saidpriming bias means in response to said switching signal from said timingdevice means.

2. The combination of claim 1, wherein said timing device means includesa timing capacitor, a timing resistor connected in series with saidtiming capacitor across said first and second terminals; a dischargecircuit for said timing capacitor including a discharge resistor and adiode connected in series with said discharge resistor across saidtiming capacitor, said discharge resistor being connected to said firstterminal and said diode being poled to pass discharge current from saidtiming capacitor; and restraining means interconnecting said secondterminal and the junction of said diode and discharge resistor forpreventing said discharge circuit from operating as long as the powerpotential appears at the second terminal.

3. The combination of claim 2, wherein said restraining means is arestraining conductor.

1. In combination with an electrical plug-in circuit card carrying acircuit having at least one circuit element capable of assuming morethan one state, which element must occupy a preferred one of said statesbefore the circuit can be used, which card also carries a first terminaland a second terminal at which reference and power potentialsrespectively appear when the card is plugged-in at a working position,the improvement which comprises at least one priming bias means forapplying a signal responsive to said power potential from said secondterminal to at least one of said circuit elements to bias said oneelement to a preferred state; timing device means responsive to theappearance of said reference and power potentials at said first andsecond terminals respectively to time a time interval exceeding the timerequired for said one element to change from one to another of saidalternative states, and to produce a switching signal on the expirationof said time interval; and switching device means connected between saidpriming bias means and said timing device means for terminating thedelivery of said signal responsive to the power potential by saidpriming bias means in response to said switching signal from said timingdevice means.
 2. The combination of claim 1, wherein said timing devicemeans includes a timing capacitor, a timing resistor connected in serieswith said timing capacitor across said first and second terminals; adischarge circuit for said timing capacitor including a dischargeresistor and a diode connected in series with said discharge resistoracross said timing capacitor, said discharge resistor being cOnnected tosaid first terminal and said diode being poled to pass discharge currentfrom said timing capacitor; and restraining means interconnecting saidsecond terminal and the junction of said diode and discharge resistorfor preventing said discharge circuit from operating as long as thepower potential appears at the second terminal.
 3. The combination ofclaim 2, wherein said restraining means is a restraining conductor.